Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as memories, microprocessors, digital clock managers (DCMs), and input/output (I/O) transceivers.
Presently, FGPAs are being used to implement receivers for digital video transmitted serially over a video coaxial cable in accordance with well known standards developed by the American National Standards Institute (ANSI) and the Society of Motion Picture and Television Engineers (SMPTE). Such standards include the serial digital interface (SDI) standard for transmitting standard definition digital video, as defined by ANSI/SMPTE 259M, and the high-definition serial digital interface (HD-SDI) standard for transmitting high-definition digital video, as defined by ANSI/SMPTE 292M. The SDI standard for standard definition digital video is referred to herein as “SD-SDI”. The term “SDI” includes both HD-SDI and SD-SDI standards.
An SDI receiver includes a framer for determining where individual words begin and end in the serial data stream. In order to frame the data stream, the encoder periodically sends a unique and recognizable pattern (i.e., a bit sequence) for the framer to use as a framing reference. The unique bit sequence is referred to as a timing reference signal (TRS). In an HD-SDI data stream, each data word is 20 bits wide. The TRS symbols for HD-SDI data streams are 80 bits long, with the first 60 bits being a fixed pattern unique in the data stream. The first 60 bits of the HD-SDI TRS symbol written in 10-bit hexadecimal words is “3FF 3FF 000 000 000 000” (i.e., twenty “1” bits followed by forty “0” bits). In an SD-SDI data stream, each data word is 10 bits wide. The TRS symbols for SD-SDI data streams are 40 bits long, with the first 30 bits being a fixed pattern unique in the data stream. The first 30 bits of the SD-SDI TRS symbol written in 10-bit hexadecimal words is “3FF 000 000” (i.e., ten “1” bits followed by twenty “0” bits).
Present SDI receivers use various pattern matching circuits to detect TRS symbols. Due to the length of the TRS symbol in either HD-SDI or SD-SDI data streams, such pattern matching circuits require a significant amount of logic to implement. Such pattern matching circuits become even more complex for multi-rate SDI decoders capable of decoding both SD-SDI and HD-SDI data streams. This presents a significant challenge to FPGA designers, since there may be insufficient logic resources available in the fabric to implement an SDI receiver, in particular, multiple SDI receivers. In addition, it may be desirable to save logic resources within an FPGA to implement various video processing functions along with one or more SDI receivers.
Accordingly, there exists a need in the art for a method and apparatus that detects a bit sequence in a data stream using a reduced amount of logic.